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Controlled available bit rate service in an ATM switch
| Details |
Inventors: Jones, Trevor;
Assignee: Ahead Communications Systems, Inc. (Middlebury, CT)
Primary Examiner: Jung; Min
Assistant Examiner:
Attorney, Agent or Firm: Gordon; David P., Jacobson; David S., Gallagher; Thomas A.
An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established, a FIFO (32) for each priority level, and a traffic shaping FIFO (34) for pointers to ABR cells. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). Pointers to ABR cells with onward transmission times are pushed into the traffic shaping FIFO (34). The arbitration FIFOs (32) are examined according to a schedule and cells are popped from VC FIFOs (30) according to priority for exit from the controller (12). A leaky bucket processor (22) calculates an average output cell rate OCR and ABR cells are popped from VC FIFOs out of turn if the MCR for the ABR VC exceed the OCR. |
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DETAILED DESCRIPTION It is therefore an object of the invention to provide an ATM switch with means for controlling the flow of ABR cells through the switch.
It is also an object of the invention to provide an ATM switch with means for controlling the flow of ABR cells through the switch which guarantees the MCR bandwidth for all ABR VCs.
It is another object of the invention to provide an ATM switch with means for controlling the flow of ABR cells through the switch which provides an accurate and fair ER for each ABR VC.
In accord with these objects which will be discussed in detail below, an ATM switch according to the invention includes a plurality of slot controllers each having at least one external network link and a link to a switch fabric, the slot controllers receiving ATM cells from the network and transmitting cells to other slot controllers via the switch fabric and receiving cells from the switch fabric and transmitting cells onto the network.
Each slot controller is provided with an input cell processor, an output cell processor, and a plurality of FIFO buffers, one cell FIFO for each VC established on the switch, one arbitration FIFO for each priority level, and a traffic shaping FIFO.
The traffic shaping FIFO is preferably configured as a leaky bucket and is provided with a look-up table for storing the MCRs of the ABR VCs.
According to the methods of the invention, when a cell enters a slot controller, the cell header is examined to determine the VCI and the priority level.
The slot controller examines the switch fabric to find a path for the VC, selects a VC FIFO for the VC, pushes the cell into the VC FIFO, increments a counter for the VC FIFO, and, if the VC FIFO was previously empty, writes a pointer to the arbitration FIFO for the priority level of the cell FIFO.
The arbitration FIFOs are examined according to a schedule and cells are popped from VC FIFOs according to priority for exit from the slot controller as described in co-owned International Application Number PCT/US96/15737
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Telecommunications 
