Dynamic memory

DETAILED DESCRIPTION An object of the present invention is to provide a memory device which enables an increase in a relative accuracy of the capacities of memory cells and full-size dummy cells.
Another object of the present invention is to provide a memory device which consumes a reduced quantity of power.
Still another object of the present invention is to provide an integrated circuit memory device which can be manufactured easily.
A further object of the present invention is to provide an integrated circuit memory device which has full-size dummy cells that enable the wiring of the dummy cell portion of the device to be simplified.
Other object of the present invention is to provide an integrated circuit memory device which has full-size dummy cells, and which enables a so-called cold start without the need of preparation cycles (usually eight cycles) setting the initial conditions when the power source circuit is closed.
Other object of the present invention is to provide an integrated circuit memory device which performs a high-speed reading operation.
Other object of the present invention is to provide an integrated circuit memory device which has full-size dummy cells that enable the layout of the dummy cell portion of the device to be designed easily.
These and other objects as well as novel features of the present invention will become obvious from the following description in conjunction with accompanying drawings.
A representative embodiment of the invention disclosed in the specification is briefly described below.
A pair of dummy cells are short-circuited so that they are connected parallel to each other.
This means that the electric charge stored in capacitors of these full-size dummy cells is divided into two, so that it is thus possible to obtain an integrated circuit memory device provided with full-size dummy cells which have the same function as that of conventional half-size dummy cells.