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Method and apparatus for equallization in an asymmetric digital aubscriber line communications system
| Details |
Inventors: Johnson, Terence L.; Higashi, Albert H.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Vo; Don N.
Assistant Examiner: Phu; Phuong
Attorney, Agent or Firm: Polansky; Paul J., Hill; Daniel D.
An equalizer (106, 146) for use in systems such as an asymmetric digital subscriber line (ADSL) transceiver (5) reduces the number of calculations required for updating the equalizer coefficients. The equalizer (106, 146) takes advantage of the substantially symmetrical phase and amplitude distortion of the signal constellation, which causes both the amplitude and the phase relationship of the calculated error term for each constellation point to be equal. Instead of performing a full complex multiplication, the equalizer (106, 146) uses some but not all of the product terms between the real and imaginary components of the calculated error term and the conjugate of the received data estimate in the coefficient update calculation. The result is then scaled to account for the missing terms. The resulting equalizer (106, 146) requires fewer calculations for coefficient updating. |
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DETAILED DESCRIPTION OF THE DRAWINGS Generally, the present invention provides an adaptive equalizer in an ADSL system that reduces the number of calculations required for updating equalizer coefficients.
The equalizer reduces the number of calculations by taking advantage of the substantially symmetrical phase and amplitude distortion of the signal constellation, which causes both the amplitude and the phase relationship of the calculated error term for each constellation point to be equal.
Therefore, it is only necessary to use either the real or imaginary term of either the calculated error term or the conjugate of the received data estimate in the coefficient update calculation.
FIG.
2 illustrates an ADSL transceiver 5 in accordance with the present invention.
ADSL transceiver 5 is a single integrated circuit which includes a DSP core 60, a memory 64, a voltage controlled oscillator (VCXO) 66, a host processor interface (HPI) 68, a plurality of DSP peripherals 69, a digital interface 70, and an analog front-end (AFE) 78.
Note the terms "analog front end" and "analog and line interface" are used interchangeably in this specification.
Digital interface 70 includes a configuration register 71 storing a control bit 72 labeled "CONRT".
DSP peripherals 69 are hardware peripherals including a fast Fourier transform (FFT) module 73, a circular echo synthesis (CES) module 74, and a time domain equalizer (TEQ) module 76.
In the illustrated embodiment, the transceiver architecture is designed using a digital signal processor (DSP) core.
It should be noted however that other types of processor cores could also be implemented.
Peripheral modules, or processing elements, of the transceiver communicate with the DSP processor and are implemented as peripheral modules to the DSP processor.
The DSP processor may access each of the peripheral modules through a standard memory -read/write operation or through one of six programmable DMA channels.
The DSP processor core may be implemented as a core of a DSP56301 single chip DSP, which is available from Motorola, Inc
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Telecommunications 
