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Power factor correction system
| Details |
Inventors: Curtiss, William P.; Colley, III, William C.;
Assignee: The Charles Stark Draper Laboratory, Inc. (Cambridge, MA)
Primary Examiner: Beha, Jr.; William H.
Assistant Examiner:
Attorney, Agent or Firm: Kenway & Jenney
A discrete-time, closed loop power factor corrector system controls the coupling of a delta-connected switched capacitor array to a 3- or 4-wire power line which may have time-varying, unbalanced, inductive loads. For inductive loads that cannot be exactly compensated with a delta-connected capacitance, the corrector system minimizes the total RMS reactive current drawn from the power line. |
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DETAILED DESCRIPTION Briefly, a power factor correction (PFC) system in accordance with the present invention is coupled to at least n power lines of an n phase power distribution system.
The PFC system includes an N-stage switched capacitor array, where N is an integer.
Each stage includes n capacitor networks where each capacitor network is associated with a pair of the power lines.
The capacitor networks of each stage are each characterized by a predetermined capacitance for that stage.
Each of the capacitor networks includes an associated capacitor switch which is responsive to an applied trigger signal for selectively coupling that capacitor network across its associated power lines.
A feedback network is also coupled to the power lines and includes a power factor detector which controls the generation of the trigger signals so that the power factor at the power lines is substantially optimally close to one, even though local loads may be unbalanced.
For an n-phase closed loop power factor correction system, during the first cycle and for all subsequent cycles, the power factor correction system measures the residual n reactive power terms (each quadrature line current times its corresponding line-to-neutral voltage) during one cycle.
The resultant residual or error signals are representative of the change in reactive power since that last correction.
The PFC system then uses this error signal to determine the capacitance to be added to or subtracted from the respective phases of the capacitor array during the next correction cycle.
Between power factor correction cycles, the actual power factor is detected and used in determining the n independent line-to-line capacitance changes required to correct the power factor.
These incremental values are summed with the previous values to compute the new desired values.
At a correction time, trigger signals, representative of the new values which are to be switched from the capacitor array are applied by way of an interface to the various stages of the array
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Telecommunications 
