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 Receiver for bandspread signals

Details
Inventors: Beier, Wolfgang;
Assignee: Standard Elektrik Lorenz AG (Stuttgart, DE)
Primary Examiner: Cangialosi; Salvatore
Assistant Examiner:
Attorney, Agent or Firm: Christie, Parker & Hale

An improved receiver for modulated bandspread carrier signals is disclosed. The invention includes an antenna for intercepting a plurality of modulated carrier signals bandspread at a first clock rate; a radio frequency section in communication with the antenna for selecting a received signal from the plurality of signals; and an intermediate frequency section in communication with the radio frequency section for converting the received signal to an intermediate frequency signal. The intermediate frequency signal is digitized and multiplied by a pseudo-random code stored in a first memory for demodulation. Successive demodulation products are added, stored and used to provide in-phase (I) and quadrature (Q) signals. Means are provided to for utilizing the I and Q signals to control the rate and the timing of the multiplication of the digitized signal with the pseudo-random code stored in the first memory.

DETAILED DESCRIPTION What is claimed is: 1.
A receiver for modulated bandspread carrier signals comprising, in combination: an antenna for intercepting a plurality of modulated carrier signals bandspread at a first clock rate; a radio frequency section in communication with said antenna for selecting a received signal from said plurality of signals; an intermediate frequency section in communication with said radio frequency section for converting said received signal to an intermediate frequency signal; digitizing means connected to said intermediate frequency section for digitizing said intermediate frequency signal, for digitizing means includes means for linearly dividing the amplitude range of said intermediate frequency signal into a number of subranges and for assigning consecutive digital numbers to said subranges; first multiplication means connected to said digitizing means for demodulating said digitized signal with a pseudorandom code stored in a first memory of said receiver; register means for adding successive products provided by said first multiplication means; means for operating on the output of said register means to provide in-phase (I) and quadrature (Q) signals, including second multiplication means adapted to multiply said sum stored in said register by a first signal from a first clock pulse generator, first summing means for summing the output of said second multiplication means, the output of said first summing means having the form: I=-Z(O)+2Z(pi)-Z(2pi), third multiplication means adapted to multiply said sum stored in said register by a second signal from said first clock pulse generator, said first signal being offset from said second signal from said first clock pulse generator by a predetermined phase shift of pi/2, and second summing means for summing the output of said third multiplication means, the output of said second summing means having the form: Q=-Z(O)+2Z(pi/2)-2Z(3pi/2)+Z(2pi); and control means for utilizing said I and Q signals to control the timing of the multiplication of said digitized signal with the pseudo-random code stored in said first memory



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