Tamperproof arrangement for an integrated circuit device

DETAILED DESCRIPTION In accordance with the present invention, a novel tamperproof arrangement for an integrated circuit is shown.
A tamperproof arrangement for an integrated circuit device includes an integrated circuit package and its associated lid.
An integrated circuit die is affixed to the integrated circuit package by die attach material.
Sensors are located throughout the integrated circuit die and integrated circuit package and lid.
These sensors detect an attempt to physically or electronically tamper with critical information included in the integrated circuit die.
The sensors produce a tampering signal.
Responsive to this tampering signal circuitry clears or zeroizes all of the critical information included in the integrated circuit die.
A method for tamperproofing an integrated circuit device includes the following steps.
Critical circuitry containing sensitive information is segregated from non-critical circuitry on the integrated circuit die.
The critical circuitry is located toward the center of the integrated circuit die to protect the sensitive information from disclosure.
Temperature sensors are provided on the integrated circuit die to sense changes in temperature.
Radiation sensors are also provided on the integrated circuit die to sense changes in radiation level.
The sensitive information is cleared if changes in the radiation level or temperature of the integrated circuit die are detected by the sensors.