Vector processor

DETAILED DESCRIPTION What is claimed: 1.
A vector processor for determining the respective values of selected bits of vector elements of a vector in response to a single vector instruction in one machine cycle, comprising: (a) vector register means for storing a vector having a plurality of vector elements each including a plurality of bits; (b) extract condition register means for storing extract condition data including a number of bits, wherein a selected plurality of the bits of said extract condition data all have a first binary value and the remaining bits of said extract condition data all have a second binary value; and (c) operation means coupled to said vector register means and said extract condition register means for effecting a logical operation between each vector element of a vector in said vector register means and said extract condition data in said extract condition register means and for determining as a result of said logical operation whether all selected bits in each vector element are "0", "1" or a mixture of "0" and "1" bits based on a comparison between said all selected bits and a reference pattern.
2.
A vector processor according to claim 1, wherein said operation means includes means for storing results of said logical operations for the respective vector elements of said vector in said extract condition register means as extract condition data.
3.
A vector processor according to claim 1, wherein said operation means comprises a first operation unit including means for carrying out an AND operation between the bits of each of the vector elements in a vector stored in said vector register means and extract condition data in which said first binary value is "1" and said second binary value is "0", and first means for determining that all selected bits of a respective vector element are "0" when all operation results of said AND operation for the vector element are "0".
4.
A vector processor according to claim 1, wherein said operation means further comprises a second operation unit including means for carrying out an OR operation between the bits of each of the vector elements in a vector stored in said vector register means and extract condition with a bit position to data in which said first binary value is "0" and said second binary value is "1", and means for determining that all selected bits of a respective vector element are "1" when all operation results of said OR operation for the vector element are "1"