Video signal processing apparatus for separating an image of a moving object from video signals

DETAILED DESCRIPTION OF THE INVENTION Referring now to FIGS.
1 through 3, a preferred embodiment will be explained.
A video signal 2 obtained by a television camera 1 is supplied to a contour image signal generating circuit 3.
The circuit 3 generates a binary contour signal 4 of about 1 volt peak to peak from the video signal 2.
The contour signal 4 is stored in a memory circuit 7 during a high level period (which corresponds to one field period) of memory control signal 3b of FIG.
3.
The memory control signal 3b is generated in synchronism with vertical driving pulses 3a which are obtained by a synchronizing separator circuit 18 of FIG.
1.
The contour signal 4 in the next field is also stored in a memory circuit 8 during high level period of memory control signal 3c of FIG.
3.
The output signals from the memory circuits 7 and 8 are added logically by an OR circuit 9 to generate a delayed contour signal 10 which is supplied to one of the input terminal of a gate circuit 11.
A gate signal 3d of FIG.
3, which corresponds to the followed field period to the field period 3C of FIG.
3, obtained by the synchronizing separator circuit 18 is supplied to a gate circuit 5 and the gate circuit 11.
Therefore, the contour signal 4 from the contour image signal generating circuit 3 and the delayed contour signal 10 from an operating circuit 6, which is composed of the memory circuits 7, 8 and OR circuit 9, are supplied to a contour extracting circuit 12 during the period of the gate signal 3d of FIG.
3.
The contour extracting circuit 12 is composed of an EXCLUSIVE OR circuit 13 and an AND circuit 14.
The contour signal 15 of the moving object extracted from the contour extracting circuit 12 is output during the period of the gate signal 3d and amplified to a certain level by an amplifier 16.
The output signal 25 from the output terminal 17 of the amplifier 16 is supplied to a track control circuit 22 to generate camera control signal X and Y.
The track control circuit 22 will be discussed with reference to FIG