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Divisional operation system for obtaining a quotient by repeated subtraction and shift operations
| Details |
Inventors: Miyoshi, Akio;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Foley & Lardner, Schwartz, Jeffery, Schwaab, Mack, Blumenthal & Evans
A divisional operation is performed by the invention, using three registers. The higher order digits or figures of dividend are given to the first register and the lower order digits or figures thereof are given to the second register. In addition, a divisor is given to the third register. Subtraction is performed between the content of the first register and the content of the third register. On the basis of the sign of the result, the quotient is determined. Every time subtraction is performed, a shift operation is conducted in the first and second registers. The quotient is stored in the second register from the least significant bit thereof. In such a shift operation, data of 1 bit is transferred from the most significant bit of the second register to the least significant bit of the first register. Where the data of 1 bit thus transferred represents "1" when the operation is completed, it is detected that division is in an overflow state. |
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DETAILED DESCRIPTION An object of this invention is to provide a divisional operation system which has saved an extra operation to attain a high operation speed.
To achieve the above object, this invention provides a divisional operation system comprising a first register for storing higher order digits or figures of dividend, a second register for storing lower order digits or figures of the dividend, a third register for storing divisors, an ALU (Arithmetic and Logic Unit) for performing subtraction between the contents of the first register and the content of the third register or addition of both the contents, a divisional result generation circuit indicating that the operation result of the ALU has been negative, and an ALU function select circuit for allowing the ALU to perform addition only when the divisional result generation circuit indicates a negative state, wherein after the ALU has completed one operation, the operation result is shifted to the left by one bit to store it into the first register and the content of the second register is shifted to the left by one bit to store the most significant bit thereof into the least significant bit of the first register, and wherein when the divisional result generation circuit indicates a negative state, "0" is stored into the least significant bit of the second register, and when otherwise, "1" is stored thereinto, thus to perform a next operation, thereafter to repeatedly perform operations a necessary number of times until a quotient is obtained at the second register, characterized in that there is further provided an overflow indication circuit for holding a bit shifted from the most significant bit of the second register after the necessary number of operations have been completed to indicate that the division is in an overflow state when the last-mentioned bit represents "1".
With the divisional operation system according to this invention, whether or not the division is in an overflow state is judged by a bit shifted from the most significant bit of the second register after necessary number of operations have been completed
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Television 
