Fast access charge coupled device memory organizations for a semiconductor chip

DETAILED DESCRIPTION What is claimed is: 1.
A charge coupled device memory organization including a plurality of storage loops, said organization comprising: a read/write station; a plurality of pairs of read and write switches, one pair for each storage loop to selectively couple that respective storage loop to said read/write station for reading and writing operations; each storage loop including a refresh amplifier; clock means to continuously supply clocking signals to drive said storage loops; and clock switch means coupled between said clock means and said storage loops to selectively couple said clock means to one or more of said storage loops to simultaneously drive said one or more of said storage loops for a plurality of successive clock signals.
2.
A charge coupled device memory organization according to claim 1 wherein: said clock switch means includes a clock switch coupled to all of said storage loops.
3.
A charge coupled device according to claim 1 wherein: said clock switch means includes a plurality of clock switches each coupled between said clock means and a corresponding storage loop.




Description:
BACKGROUND OF THE INVENTION 1.
Field of the Invention This invention relates to memory organizations formed of charge coupled devices and more particularly to fast access memory organizations for implementation on a single semiconductor chip.
2.
Background of the Invention Charge coupled devices (CCD's) are fabricated as metal-oxide-silicon (MOS) or metal-insulated-silicon (MIS) integrated circuits wherein charges are stored on the surface of a substrate by the application of voltage pulses to storage gates to form potential wells.
Signal charges may be inputted and the resultant charge packets are shifted along various points throughout the substrate of the device by the application of the proper sequence of voltage pulses to modulate the potential wells.
A particular application of charge coupled devices is that of forming serial dynamic memory arrays in which the bits are recirculating and are refreshed in closed loops