Finite field multiplier

DETAILED DESCRIPTION What is claimed is: 1.
A finite field multiplier for forming the product of two operands A and B expressed as a plurality of binary bits, where each operand is of the same length and wherein the relationship 2.
sup.
m -1 is divisible to form an integer by m+1 wherein m is the number of bits in said operands, wherein said multiplier comprises, means for receiving an A operand of the form A=a.
sub.
0 +a.
sub.
1 x+a.
sub.
2 x.
sup.
2 +a.
sub.
3 x.
sup.
3 +.
.
.
+a.
sub.
m-1 x.
sup.
m-1 means for receiving a B operand of the form B=b.
sub.
0 +b.
sub.
1 x+b.
sub.
2 x.
sup.
2 +b.
sub.
3 x.
sup.
3 +.
.
.
+b.
sub.
m-1 x.
sup.
m-1 a first transpose network means for transforming the A operand into the equivalent form A'=a'.
sub.
0 +a'.
sub.
1 r+a'.
sub.
2 r.
sup.
2 +a'.
sub.
3 r.
sup.
3 +a'.
sub.
4 r.
sup.
4 +.
.
.
+a'.
sub.
m r.
sup.
m where r.
sup.
m+1 =x.
sup.
2m-1 =1 wherein said first transpose network means is comprised of Exclusive OR gates, a second transpose network means for transforming the B operand into the equivalent form B'=b'.
sub.
0 +b'.
sub.
1 r+b'.
sub.
2 r.
sup.
2 +b'.
sub.
3 r.
sup.
3 +b'.
sub.
4 r.
sup.
4 +.
.
.
+b'.
sub.
m r.
sup.
m where r.
sup.
m+1 =x.
sup.
2m-1 =1 wherein said second transpose network means is comprised of Exclusive OR gates, a plurality of first multiplier busses connected to receive the output of said first transpose network means, a plurality of second multiplier busses connected to receive the output of said second transpose network means, a plurality of AND gate groups connected in array form to said first and second plurality of multiplier busses, a plurality of product busses, at least one Exclusive OR gate connected to each of said AND gate groups and having an output connected to one of said product busses, an output inverse transpose network connected to said product busses for producing a product ##EQU15## wherein said inverse transpose network is comprised of Exclusive OR gates and the resultant product is a sequence of m bits.




Description:
BACKGROUND OF THE INVENTION This invention relates to digital multipliers as used in the field of error correction techniques