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 Hybrid hypercube/torus architecture

Details
Inventors: Passint, Randal S.; Thorson, Greg; Galles, Michael B.;
Assignee: Silicon Graphics, Inc. (Mountain View, CA)
Primary Examiner: Chan; Eddie
Assistant Examiner: Monestime; Mackly
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4.times.8.times.4 torus topology.

DETAILED DESCRIPTION The present invention provides a scalable multiprocessor system including a plurality of processing element nodes.
Each processing element node includes at least one processor and memory.
A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology.
Routers in the scalable interconnect network route messages between the plurality of processing element nodes on the physical communication links.
The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four.



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