Slot reception synchronization circuit

DETAILED DESCRIPTION What is claimed is: 1.
A time slot reception synchronization circuit for detecting a unique word which is included in one time slot data and for receiving the one time slot data in synchronism with said unique word, comprising: time slot length data holding means having a bit-length equal to that of said one time slot data for holding received one time slot data corresponding to one time slot bit-length, said time slot length data holding means having parallel output terminals for outputting in parallel each bit of a bit pattern of a given bit range of a held time slot data, a bit-length of which is smaller than that of said time slot length data holding means and is equal to that of a bit pattern of a predetermined unique word, said parallel output terminals being provided only at bit positions corresponding to the bit positions of the given bit range of the held time slot data; detecting means for detecting whether data output from said parallel output terminals is matched with a bit pattern of a predetermined unique word and for generating a matching signal when the data output from said parallel output terminals is matched with said predetermined unique word; and means for feeding out in parallel the held time slot data from said time slot length data holding means as time slot data in response to said matching signal.
2.
A slot reception synchronization circuit as set forth in claim 1, wherein said detecting means includes judgement means for making judgement for matching of the bit pattern in the given bit range of said held slot data of said time slot length data holding means with the bit pattern of said unique word, per each bit.
3.
A slot reception synchronization circuit as set forth in claim 2, wherein said judgment means includes arithmetic means which performs exclusive NOR operation for each bit of the bit pattern in the given range of said hold slot data of corresponding bits of the bit pattern of said unique word.
4.
A slot reception synchronization circuit as set forth in claim 2, wherein said detection means includes adder means for adding matching results of each of the corresponding bits and allowable range detecting means for detecting whether the result of adding by said adder means falls within a preliminarily set allowance range