System for phase-locking a clock to a digital audio signal embedded in a digital video signal

DETAILED DESCRIPTION What is claimed is: 1.
A method for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising the steps of: generating a first reference frequency signal from digital audio signal samples embedded within the digital video signal by dividing the frequency of the digital audio signal samples by a divisor such that the period of the first reference frequency is greater or equal to that of phase jitter present in the digital audio signal samples; generating a second reference frequency signal from an output audio sample frequency signal, the frequency of the output audio sample frequency signal being equal to the frequency of the digital audio signal samples so that, when divided by the divisor, the frequency of the second reference frequency signal equals that of the first reference frequency signal; generating from the first and second reference frequency signals a low jitter clock control signal, the low jitter clock control signal been result of rejecting the phase jitter present in the digital audio signal samples; and generating the output audio sample frequency signal from the low jitter clock control signal.
2.
The method according to claim 1, wherein the low jitter clock control signal generating step comprises the steps of: inputting the first and second reference frequency signals into a phase detector; and filtering output from the phase detector such that the phase jitter present in the digital audio signal samples is rejected and the low jitter clock control signal is produced.
3.
The method according to claim 2, wherein the filtering step comprises the step of inputting output from the phase detector through a series of two loop filters, one of which is an adjusted bandwidth loop filter, such loop filter's bandwidth configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.
4.
The method according to claim 2, wherein the filtering step comprises the step of inputting output from the phase detector to a loop filter, such loop filter allowing for a system gain to decline to less than 1 with a phase shift not supporting oscillations at a gain of 1, and such loop filter's bandwidth is configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced