MFM data encoder with write precompensation

DETAILED DESCRIPTION The present invention is an electronic circuit for performing MFM encoding and write precompensation in one step.
It eliminates the need for analog or digital delay lines and greatly reduces the number of electronic components required.
In the present invention, data encoded according to the MFM encoding algorithm and the write precompensation encoding algorithm is stored in a read-only memory (ROM).
In order to determine the output of the encoder circuit, the bit to be encoded, the previous two encoded bits, and the next bit to be encoded are examined.
This is done with a serial-to-parallel shift register.
The four output lines of the shift register are used to address the specific locations in the ROM wherein the properly encoded data bit is stored.
A fifth address line to the ROM accesses the encoded data that has been write precompensated when write precompensation is required.
The encoded data bits stored in the ROM are each composed of eight equal time sections.
Four sections represent a logical one and four represent a logical zero.
Which of the four sections the data bit is in is determined by the write precompensation algorithm.
The eight time sections are read out of the memory in parallel form and converted back to a serial bit stream.
It is therefore the object of the present invention to provide a simple and novel circuit to convert a serial bit stream into a serial bit stream with MFM encoding and write precompensation encoding.
Other objects and advantages will become apparent to those having ordinary skill in the art upon a reading of the following description when taken in conjunction with the accompanying drawings.